The present invention generally relates to semiconductor devices and more particularly to a fabrication process of a semiconductor device having a matrix array of contacts including a pin grid array or a ball grid array and a fabrication process thereof.
With the advancement in the art of device miniaturization, recent highly integrated LSI chips generally carry a very large number of contact electrodes thereon for external interconnection. For example, there are LSI chips that carry the contact electrodes with a number of several hundreds or even one thousand.
FIG. 1A shows an example of such an LSI chip 1 of the so-called BGA (ball grid array) type in which a number of solder balls 30 are provided on a principal surface 1a thereof in a row and column formation as the contact electrodes. There are LSI chips of this type in which the number of the solder balls 30 exceeds 500. The solder balls 30 on the chip 1 includes power supply terminals 31 and input/output terminals 32.
It should be noted that the fabrication process of a semiconductor device such as an LSI chip 1 includes a testing process of the chip 1, wherein the testing process includes the step of mounting the LSI chip 1 on a testing board in the state that the solder balls 30 are connected electrically to test terminals on the testing board via corresponding contact pins. In the case of recent LSI chips carrying a very large number of solder balls 30 on the chip principal surface 1a, it should be noted that the number of the solder balls 30 can exceed the number of the test terminals provided on the testing board, and there arises a problem in that the testing is not possible for all of the solder balls 30 on the chip 1.
In order to overcome the shortcomings of such a conventional testing process, it is proposed to carry out the testing process according to the process shown in the flowchart of FIG. 2.
Referring to FIG. 2, a number of regions R1-R4 are defined in the step S21 on the principal surface 1a of the LSI chip 1 by boundaries L1 and L2 as indicated in FIG. 1B, such that the number of the solder balls 30 does not exceed the number of the test terminals of the testing board in any of the regions R1-R4. As will be explained later in detail, the test of the LSI chip 1 is conducted for each of the regions R1-R4, while the regions R1-R4 are defined arbitrary. This means that the number or arrangement of the solder balls 30 as well as the type of the terminals provided by the solder balls may be different in each of the regions R1-R4.
Next, one of the regions R1-R4 is selected for testing in the step S22, and a testing board 2a for the region R1 is mounted on a testing apparatus in the step S22b, as will be explained with reference to FIG. 3A. Further, a test program corresponding to the selected region is loaded in the step S23 on a computer cooperating with the testing board.
After the step S23, the LSI chip 1 is mounted on the testing board in the step S24.
FIGS. 3A and 3B show the examples of mounting the LSI chip 1 on the testing board 2a in a bottom view, wherein FIG. 3A shows the LSI chip 1 mounted on the testing board 2a while FIG. 3B shows the LSI chip 1 mounted on a testing board 2b. 
Referring to FIG. 3A, the testing board 2a carries thereon test terminals 33 corresponding to the power terminals 31 or the input/output terminals 32 on the selected region R1 of the LSI chip 1, along a periphery of the testing board 2a in electrical connection with contact pins that are provided on the testing board 2a or 2b in rows and columns in correspondence to the solder balls 30 on the LSI chip 1, and the testing is conducted in the step S25 in the state of FIG. 3A while using the test program loaded in the test computer previously in the step S23 of FIG. 2. In FIG. 3A, it should be noted that the contact pins on the testing board 2a are connected to respective, corresponding test terminals 33 via a wiring pattern 34.
Based on the result of the testing in the step S25, a discrimination step S26 is conducted for discriminating whether or not the tested region R1 of the LSI chip 1 is defect-free, and if the result is NO, the chip 1 is discarded in the step S27.
Next, in the step S28, a discrimination is made whether or not all the LSI chips 1 are tested, and if the result is NO, the tested LSI chip 1 is dismounted from the testing board 2a and a next LSI chip 1 is mounted such that the region R1 of the next LSI chip 1 is tested.
Further, in the step S29, a discrimination is made whether or not all the regions R1-R4 of all the LSI chips 1 are tested, and if the result is NO, the first LSI chip 1 is mounted on the second testing board 2b of FIG. 3B for testing of the region R2. It should be noted that the testing board 2b is designed for testing the region R2 and carries a wiring pattern 34′ different from the wiring pattern 34 provided on the testing board 2a for testing the region R1. Thereby, the steps S22-S29 are repeated for the all the regions R2-R4.
However, the foregoing testing process has a drawback in that it is necessary to provide a number of testing boards 2a and 2b in correspondence to arbitrarily defined regions R1-R4. It should be noted that the wiring pattern 34 has to be changed in each of the testing boards in correspondence to the selected regions R1-R4 even though the testing boards may have the same row and column arrangement of the contact pins. Further, the testing program has to be changed in each of the regions R1-R4 and hence in each of the testing boards. Thereby, the cost of the testing of the LSI chip increases inevitably.
Further, the foregoing testing process has a drawback in that it requires a large number of testing steps including loading and unloading of the testing programs, mounting and dismounting of the LSI chips, and the like.